way to generate pseudo-random data inside of an FPGA. A LFSR or Linear Feedback Shift Register is a quick and easy Here is the full table of all LFSR patterns published by Xilinx. I based this on an XNOR implementation to allow the FPGA to start up in an all-zero state on the LFSR. Therefore, for 3 bits, it takes 2 3-1=7 clocks to run through all possible combinations, for 4 bits: 2 4-1=15, for 5 bits: 2 5-1=31, etc. It uses polynomials (which is the math behind the LFSR) to create the maximum possible LFSR length for each bit width. The VHDL and Verilog code creates any N-Bit wide LFSR that you desire. That pattern is all 0’s when using XOR gates, or all 1’s when using XNOR gates as your feedback gate. Therefore there is only one pattern that cannot be expressed using an LFSR. If you think about it, all possible patterns of something that is N-bits long is 2 N. The longest possible number of iterations for an LFSR of N-bits is 2 N-1. Longer LFSRs will take longer to run through all iterations. The maximum possible number of iterations of any LFSR = 2 Bits-1.Since 1 XNORed with 1 will always produce 1, the LFSR will stop running.
A pattern of all 1’s cannot appear when the taps use XNOR gates.
Since 0 XORed with 0 will always produce 0, the LFSR will stop running.
You can figure out the next state by knowing the position of the XOR gates as well as the current pattern. If you need to change the taps on-the-fly without disturbing the contents of the shift registers, this could limit what architectures you can use and some of the optimizations you might be able to make. Depending on the architectural features of the FPGAs and your design constraints, one option may make more sense than the others.Īnother consideration is constraints on how the shift register taps are changed. Dual-port RAMs are another option, especially for longer shift registers or for multiple parallel shift registers with identical taps. It is possible to make variable length shift registers with large MUXes, though this could consume a lot of logic resources. If you aren't using Xilinx FPGAs, then it might be advisable to look at the programming manuals to figure out what sort of shift register features are supported. With a bit of additional logic it should be possible to implement this with fewer registers, though there could be some disruption when changing the tap selection under certain conditions. What I would recommend is using 6 of these 32-bit shift registers as three 63-bit registers in parallel, one fixed at 63 bits and the other two for the variable taps. If you are using Xilinx FPGAs, the LUTs can be configured as 32-bit shift registers (SR元2), each with one adjustable tap.
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